SR=NORMAL_MODE, CS=STOP, MMC=ENABLED, I=NORMAL, CE=DISABLED
Controls dynamic memory operation.
| CE | Dynamic memory clock enable. 0 (DISABLED): Disabled. Clock enable of idle devices are deasserted to save power (POR reset value). 1 (ENABLED): Enabled. All clock enables are driven HIGH continuously.[1] |
| CS | Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode. 0 (STOP): Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode. 1 (RUN): Run. CLKOUT runs continuously (POR reset value). |
| SR | Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2] 0 (NORMAL_MODE): Normal mode. 1 (SELF_REFRESH): Self-refresh. Enter self-refresh mode (POR reset value). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| MMC | Memory clock control. 0 (ENABLED): Enabled. CLKOUT enabled (POR reset value). 1 (DISABLED): Disabled. CLKOUT disabled.[3] |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| I | SDRAM initialization. 0 (NORMAL): Normal. Issue SDRAM NORMAL operation command (POR reset value). 1 (MODE): Mode. Issue SDRAM MODE command. 2 (PALL): PALL. Issue SDRAM PALL (precharge all) command. 3 (NOP): NOP. Issue SDRAM NOP (no operation) command) |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |